1. Field of the Invention
The present invention relates to an access key generating apparatus, and more particularly, to an access key generating apparatus and an information processing apparatus, which are capable of generating an access key used to control memory access from a peripheral device.
2. Description of the Related Art
In a system in which an input/output address is mapped to a physical memory of a processor, when access to the memory is made from a peripheral device, if no restriction is provided, malicious user software may illegally access an address area. For example, such a problem may occur when a direct memory access controller (DMAC) is opened to user software. For the purpose of addressing this problem, for example, a processor cell (or Cell Broadband Engine) is provided with an address conversion table having pairs of access keys of 11 bits, which are possessed by a peripheral device, and address areas, which are accessible by the peripheral device. Since this address conversion table is set by privileged software, control is made to prevent the peripheral device from accessing an address area not permitted by the privileged software.
However, if such a control is implemented for a general bus system, the following problem may occur. That is, for example, in the case of a system using a peripheral component interconnect (PCI) bus, since each device identifier identifying devices in the system individually is composed of 16 bits, bit length is insufficient in an access key of 11 bits.
On the other hand, there are techniques that allocate device identifiers of peripheral devices as parts of an access key and address. For example, there has been proposed an information processing apparatus which determines whether or not access is permitted by using lower 11 bits of a device identifier as an access key and corresponding upper 5 bits to a segment number and a page number [for example, see Pamphlet of International Publication No. 2007/129482 (Pages 7 to 9)].